1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a boundary scan circuit, and more particularly to a semiconductor integrated circuit with a boundary scan circuit composed of a logic circuit having different logic levels.
2. Description of the Related Art
One conventional boundary scan path (hereinafter referred to as "BSP") that has heretofore been implemented in a semiconductor integrated circuit will be described below with reference to FIG. 1 of the accompanying drawings.
In FIG. 1, an internal logic circuit 302 of a semiconductor integrated circuit has data input pins 305-308 and data output pins 309-312. A BSP includes testing circuits 313-320 including registers are connected in series between the data input pins 305-308 and data output pins 309-312. Data are inputted serially to a test data input pin 303 of the testing circuits 313-320, and parallel data produced from the inputted data are applied to the internal logic circuit.302, which is to be tested. Parallel data, indicative of the test results, are outputted serially from a test data output pin 304 of the testing circuits 313-320. In this manner, the semiconductor integrated circuit has been tested by the BSP. For further details, see "Nikkei Electronics" No. 488, pages 314 to 320, for example.
Another conventional BSP for a semiconductor device having a plurality of logic levels will be described below with reference to FIG. 2 of the accompanying drawings.
In FIG. 2, the semiconductor device has three logic levels, i.e., PECL, CMOS, GTL levels, and there are no limitations on the arrangement of pins due to the logic levels. The PECL level is the level of an ECL circuit that operates with a positive power supply, whereas ECL circuits normally operate with a negative power supply.
The semiconductor device shown in FIG. 2 has an internal logic circuit 402, data input pins 405-408, data output pins 409-412, a test data input pin 403, a test data output pin 404, and testing circuits 413-420 which are identical to the internal logic circuit 302, the data input pins 305-308, the data output pins 309-312, the test data input pin 303, the test data output pin 304, and the testing circuits 313-320. Inasmuch as the semiconductor device has three different logic levels and there are no limitations on the arrangement of pins due to the logic levels, as described above, level converters 421-427 for converting the levels are inserted in paths which connect the testing circuits 413-420 in series to each other.
With no limitations on the arrangement of pins due to the logic levels, the number "n" of inserted level converters is in the range of:
Number of level types.ltoreq.n.ltoreq. number of device pins, and hence depends on the number of level types of adjacent pins.
FIG. 3 of the accompanying drawings shows still another conventional BSP for a semiconductor device having three logic levels, i.e., PECL, CMOS, GTL levels, and limitations on the arrangement of pins due to the logic levels.
The conventional BSP shown in FIG. 3 is similar to the conventional BSP shown in FIG. 2 except that no level converters are inserted between the data input pins 405, 406 and also between the data output pins 418, 419 where the levels are the same.
With limitations on the arrangement of pins due to the logic levels, the number "n" of inserted level converters is in the range of:
(Number of level types) -1.ltoreq.n.ltoreq. (number of device pins) -1, and hence can be smaller. To reduce the number "n" of inserted level converters, however, it is necessary to position pins of the same level adjacent to each other.
In the semiconductor device with different logic levels and with no limitations on the arrangement of pins due to the logic levels, the number of level converters inserted in the BSP is very large, and may be equal to the number of pins at maximum. Consequently, the area taken up by the level converters is large, resulting in a large chip size.
In the semiconductor device with different logic levels and with limitations on the arrangement of pins due to the logic levels, the number of level converters inserted in the BSP may be smaller than that in the semiconductor device with no limitations on the arrangement of pins due to the logic levels. The more the limitations on the arrangement of pins due to the logic levels, the smaller the number of level converters inserted in the BSP.
However, the limitations on the arrangement of pins due to the logic levels greatly reduce the freedom of device design. In view of limitations on simultaneous operation needed by the positioning of pins of the same level adjacent to each other, it is necessary to further reduce the freedom of device design. Accordingly, the freedom of device design is limited though the chip size is not increased.